ASICLAND는 고객사가 요청하는 Application에 맞게 합성부터 GDS Out까지 다양한 공정의 Design Service를 제공합니다.
Spec to GDS
RTL to GDS
Netlist to GDS
DFT (Design For Test)
Auto P&R
Digital IP
Hardening
Hard IP (GDS) merge
Chip Test
ASICLAND 고객사가 요청하는 Application에 맞게 합성부터 GDS Out 까지 다양한 공정의 Design Service 를 제공합니다.
Synthesis for Power Optimization
Topographic Synthesis for Optimization
Equivalence Check
Low power methodology
Scan Design & ATPG
Memory BIST & BIRA
JTAG Test
IP Integration Test
Early Engagement
PowerPlan & FloorPlan
CTS & CTO
Timing Optimization
OCV (On Chip Variation) analysis
Power, SI and timing aware implementation
Low power methodology
DFM advisor - CMP/LPC analysis and fixing
LVS & DRC
Power consumption Analysis
Tape Out
Chip 제작
Package Service
Test Service
Reliability Test Service