Contact
Design
Service
ASICLAND provides the diverse processes of design services covering from the synthesis to GDS Out based on the application that our clients request.
Overview
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Spec to GDS
RTL to GDS
Netlist to GDS -
DFT (Design For Test)
- SCAN
- JTAG
- ATPG
- Memory
BIST / BIRA
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Auto P&R
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Digital IP
Hardening -
Hard IP (GDS) merge
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Chip Test
- IP test circuit
- Test pattern integration
Business Scope
ASICLAND provides a broad range of design services that cover synthesis to GDS Out based on the type of application that our clients request.
Synthesis for Power Optimization
Topographic Synthesis for Optimization
Equivalence Check
Low power methodology
Scan Design & ATPG
Memory BIST & BIRA
JTAG Test
IP Integration Test
Early Engagement
PowerPlan & FloorPlan
CTS & CTO
Timing Optimization
OCV (On Chip Variation) analysis
Power, SI and timing aware implementation
Low power methodology
DFM advisor - CMP/LPC analysis and fixing
LVS & DRC
Power consumption Analysis
Tape Out
Chip manufacture
Package Service
Test Service
Reliability Test Service
