Synthesis for Power Optimization
Topographic Synthesis for Optimization
Equivalence Check
Low power methodology

Scan Design & ATPG
Memory BIST & BIRA
JTAG Test
IP Integration Test

Early Engagement
PowerPlan & FloorPlan
CTS & CTO
Timing Optimization
OCV (On Chip Variation) analysis
Power, SI and timing aware implementation
Low power methodology
DFM advisor - CMP/LPC analysis and fixing
LVS & DRC
Power consumption Analysis

Tape Out

Chip manufacture

Package Service
Test Service
Reliability Test Service