為符合客戶方所提出的應用程序要求, ASICLAND提供從合成到GDS Out多樣化工序的設計服務。
Spec to GDS
RTL to GDS
Netlist to GDS
DFT (Design For Test)
Auto P&R
Digital IP
Hardening
Hard IP (GDS) merge
Chip Test
為符合客戶方所提出的應用程序要求,ASICLAND提供從合成到
GDS Out多樣化工序的設計服務。
Synthesis for Power Optimization
Topographic Synthesis for Optimization
Equivalence Check
Low power methodology
Scan Design & ATPG
Memory BIST & BIRA
JTAG Test
IP Integration Test
Early Engagement
PowerPlan & FloorPlan
CTS & CTO
Timing Optimization
OCV (On Chip Variation) analysis
Power, SI and timing aware implementation
Low power methodology
DFM advisor - CMP/LPC analysis and fixing
LVS & DRC
Power consumption Analysis
Tape Out
Chip manufacture
Package Service
Test Service
Reliability Test Service